1. Field of the Invention
The present invention relates to a non-volatile memory low voltage and high speed erasure method, and in particular to a non-volatile memory low voltage and high speed erasure method, that can be used to generate adequate hot holes to proceed with low voltage and high speed erasure operations by means of reverse bias and changed gate voltage.
2. The Prior Arts
Presently, Complementary Metal Oxide Semiconductor (CMOS) technology is frequently utilized in producing Application Specific Integrated Circuit (ASIC), and in the present age of Computer & Information technologies, the Electrically Erasable Programmable Read Only Memory (EEPROM) is widely utilized in various electronic products for its non-volatile memory capability of being electrically programmable and erasable, and also data stored therein will not disappear after power is shut down.
In general, the non-volatile memory is programmable, that can be used to store charges for changing the gate voltage of the transistor of the memory, or not to store charges for retaining the original gate voltage of the transistor of the memory. The purpose and functions of an erasure operation is to remove all the charges stored in the non-volatile memory, so that all the non-volatile memory will return to the original gate voltage of the transistor of the memory. In a structure of non-volatile memory of the prior art, usually, the erasure voltage utilized is in the excess of 10V, and the time required for erasure is in the order of milli-second (ms), such that not only the voltage raising area could cause the increase of cost, but it also can not achieve the purpose of low voltage and high speed erasure. Besides, in the advanced technology of producing erasable non-volatile memory, in order to reduce the influence of an oxide layer to the erasure voltage and time, a tunneling oxide layer has to be added, such that it would not only result in difficulties in manufacturing, but it could also increase production cost.